Each of the quizzes took place in recitation one day after the listed lecture.
Abbreviations
CMOS = complementary metal-oxide-semiconductor
ALU = arithmetic logic unit
OS = operating system
| LEC # | TOPICS | LABS | QUIZZES |
|---|---|---|---|
| 1 | Course overview and mechanics, basics of information | ||
| 2 | Digital abstraction, combinational logic, voltage-based encoding | ||
| 3 | CMOS technology, gate design, timing | ||
| 4 | Canonical forms; synthesis, simplification | ||
| 5 | Sequential logic | Lab 1 (CMOS) due | Quiz 1 |
| 6 | Storage elements, finite state machines | ||
| 7 | Synchronization, metastability | Lab 2 (Adder) due | |
| 8 | Pipelining; throughput and latency | ||
| 9 | Case study: multipliers | Lab 3 (ALU) due | |
| 10 | Beta instruction set architecture, compilation | Quiz 2 | |
| 11 | Machine language programming issues | ||
| 12 | Models of computation, programmable architectures | Lab 4 (Turing machine) due | |
| 13 | Stacks and procedures | ||
| 14 | Non-pipelined Beta implementation | Lab 5 (Assembly language) due | |
| 15 | Multilevel memories; locality, performance, caches | ||
| 16 | Cache design issues | Quiz 3 | |
| 17 | Virtual memory: mapping, protection, contexts | ||
| 18 | Virtual machines: timesharing, OS kernels, supervisor calls | Lab 6 (Beta) due | |
| 19 | Devices and interrupt handlers, preemptive interrupts, real-time issues | ||
| 20 | Communication issues: busses, networks, protocols | Lab 7 (Trap handler) due | Quiz 4 |
| 21 | Communicating processes: semaphores, synchronization, atomicity, deadlock | ||
| 22 | Pipelined Beta implementation, bypassing | ||
| 23 | Pipeline issues: delay slots, annulment, exceptions | Lab 8 (Tiny OS) due | Quiz 5 |
| 24 | Parallel processing, shared memory, cache coherence, consistency criteria | ||
| 25 | Wrapup lecture | Project due |