Course Meeting Times
Lectures: 2 sessions / week, 1.5 hours / session
Tutorials: 1 session / week, 1.5 hours / session
Prerequisites
6.011 and 6.111
Topics
The course will focus on four major categories as outlined below:
- Introduction to digital communications
- Modulation and detection, vector channel representation
- Equalization
- Multi-channel systems (modulation methods, waterfiling, bit loading)
- Practical examples including 802.11a
- Coding – sequence detection, gap, convolutional and block codes
- ASIC design fundamentals
- ASIC design flow, tools, system-on-a-chip design issues
- Micro-architectures and transformations (parallelism, pipelining, folding, time-multiplexing)
- Hardware description languages: introduction to Bluespec™ and Verilog® review
- Theory and building blocks
- Fast fourier transform (theory, fast algorithms and VLSI implementations)
- Convolutional and Trellis codes, and Viterbi algorithm (theory, algorithms and VLSI implementations)
- Synchronization (phase and frequency tracking loops, algorithms and VLSI implementations)
- Block codes (Hamming, BCH, Reed-Solomon), basic theory and VLSI implementations
- Wireless channel fundamentals
- Properties and modeling (fading, Doppler effect,...)
- Channel estimation (theory and VLSI implementations)
Grading
| ACTIVITIES | PERCENTAGES |
|---|---|
| Midterm | 15% |
| Final | 25% |
|
Four major homeworks (10% each)
|
40% |
| Two minor problem sets (5% each) | 10% |
| Final presentation and write-up | 10% |
Calendar
The calendar below provides information on the courses lectures (L) and Tutorials (T) sessions.
| SES # | TOPICS | KEY DATES |
|---|---|---|
| L1 | Course overview | |
| T1 | CppSim | |
| L2 | Introduction to practical digital communications | |
| L3 | Multi-tone systems | Problem set 1 out |
| T2 | Verilog® review | |
| L4 | 802.11a transceiver architecture | |
| L5 | ASIC design |
Problem set 1 due Problem set 2 out |
| T3 | 802.11a PHY standard | |
| L6 | Micro-architectures and transformations | |
| L7 | Bluespec™ overview | Problem set 2 due |
| T4 | Bluespec™ | |
| L8 | Fast fourier transform: theory and algorithms | Problem set 3 out |
| L9 | Fast fourier transform: practical aspects and basic architectures | |
| T5 | Design flow, part 1 | |
| L10 | Fast fourier transform: advanced VLSI architectures | Problem set 3 due |
| L11 | Convolutional codes | |
| T6 | Design flow, part 2 | |
| L12 | Trellis codes | |
| Exam 1 | ||
| L13 | Viterbi algorithm | |
| L14 | Viterbi algorithm (cont.) | |
| L15 | Viterbi algorithm (cont.) | |
| L16 | Viterbi algorithm (cont.) | |
| L17 | Synchronization introduction | |
| L18 | Synchronization OFDM | |
| L19 | Synchronization: implementations | |
| L20 | Wireless channels | |
| L21 | Channel estimation | |
| L22 | Block codes: introduction | |
| L23 | Block codes: code classes and Reed-Solomon codes | |
| L24 | Block codes: implementations | |
| Exam 2 |
